(1) Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for forming a novel graded silicon nitride (Si.sub.3 N.sub.4)/silicon oxide (SiO.sub.2) (also referred to as SNO) hard mask on a substrate. This novel SNO layer improves the profile (optical fidelity) of the photoresist etch mask image used to pattern the SNO layer, and thereby improves the critical dimensions (CD) for deep submicrometer semiconductor circuits.
(2) Description of the Prior Art
As the minimum feature sizes continue to decrease to deep submicrometer (um) dimensions (0.10-0.20 um) for making Ultra Large Scale Integration (ULSI) circuits, it is necessary to further improve the fidelity of the photoresist mask images used to etch the various material layers formed on semiconductor substrates. One of these layers is the silicon nitride (Si.sub.3 N.sub.4) used as an oxidation barrier and/or hard mask on a single-crystal silicon substrate. In the conventional process a relatively thin pad oxide (e.g.,SiO.sub.2) is formed on the surface of the silicon substrate, and a Si.sub.3 N.sub.4 layer is deposited. The Si.sub.3 N.sub.4 is patterned using a photoresist mask and plasma etching to leave portions of the Si.sub.3 N.sub.4 over the device areas while removing portions on the silicon substrate surface around the device areas. A field oxide is formed around the device areas to electrically isolate the individual device areas from each other. The interposing pad oxide serves to reduce the high stress from the Si.sub.3 N.sub.4 which would otherwise cause crystalline defects in the single-crystal silicon. In early versions of the process, the field oxide was formed by thermally oxidizing the silicon in the field oxide areas, while the patterned Si.sub.3 N.sub.4 protected the device areas from oxidation. This conventional approach is commonly referred to in the industry as the LOCal Oxidation of Silicon (LOCOS) process. Unfortunately, the LOCOS process is an essentially isotropic oxidation and results in lateral oxidation under the Si.sub.3 N.sub.4 oxidation barrier mask, commonly referred to as "the bird's beak" because of it shape. This lateral oxidation is sensitive to the thickness of the pad oxide and limits the minimum feature size device areas. If the pad oxide is too thin, the stress from Si.sub.3 N.sub.4 hard mask is unacceptably high causing silicon defects, and if the pad oxide is too thick the bird's beak extends too far under the oxidation barrier mask and limits the pattern density. Kobayashi et al. in U.S. Pat. No. 5,616,401 teaches several methods of reducing the bird's beak using a graded silicon oxynitride/silicon nitride isolation oxidation mask. In U.S. Pat. No. 5,510,290 to Kwon another approach is described. Kwon etches openings in a Si.sub.3 N.sub.4 hard mask to a thin thermal silicon oxide over the field oxide areas and thermally converts the oxide to silicon oxynitride (SiON). Sidewall spacers are formed in the openings to reduce the width, and the SiON is etched to the silicon substrate, and a LOCOS is performed to crate narrow field oxides. Hyung et al. in U.S. Pat. No. 5,523,255 uses a polysilicon buffer layer between the pad oxide and the silicon nitride hard mask to reduce the length of the bird's beak. In U.S. Pat. No. 5,629,043, Inaba et al. teach a method for making a better thin Si.sub.3 N.sub.4 interelectrode dielectric layer for stacked DRAM capacitors.
An alternative approach of making a field oxide isolation which eliminates the bird's beak and increases the density of device areas is to form a field oxide isolation, commonly referred to as a shallow trench isolation (STI). This approach eliminates the bird's beak and is more desirable for deep submicrometer processing. In this method a Si.sub.3 N.sub.4 and the photoresist mask protect the device areas while the exposed silicon is anisotropically etched in the field oxide areas to form trenches having essentially vertical sidewalls. After removing the photoresist it is common practice to grow a sacrificial oxide and wet etch the oxide to remove any silicon damaged due to the plasma etching, and then a new thin oxide is grown to provide a good interface at the silicon surface. The trench is then filled with a chemical vapor deposited (CVD) silicon oxide and etched or polished back to the Si.sub.3 N.sub.4 hard mask. This STI structure circumvents the bird's beak problem and provides a planar substrate surface that is ideal for subsequent processing steps.
However, to achieve deep submicrometer feature sizes it is necessary to make reliable and reproducible photoresist mask images on the Si.sub.3 N.sub.4 hard mask. One problem associated with making reliable well shaped photoresist images is best understood by referring to the prior art of FIG. 1. In FIG. 1 a silicon substrate 10 typically has a pad oxide 12 formed on the surface to reduce stress, and then a Si.sub.3 N.sub.4 layer 14 is deposited. A blanket photoresist layer 16 is spin coated and is optically exposed and developed to leave portions of the photoresist over device areas 2 on the substrate 10, while exposing the Si.sub.3 N.sub.4 14 in the areas 4. This photoresist mask and plasma etching are then used to etch the Si.sub.3 N.sub.4 and trenches in the substrate for the STI field oxide. To etch deep submicrometer structures the patterned photoresist layer 16 should have im essentially vertical profile down to the Si.sub.3 N.sub.4 hard mask layer 14. However, because of interactions between the patterned photoresist layer 16 and the nitride layer when exposed with the short wavelength deep ultraviolet (DUV) light, unwanted undercutting or lateral recessing 6 occurs in the photoresist at the Si.sub.3 N.sub.4 surface during photoresist developing. These recesses 6 make it difficult to etch reliable submicrometer images in the Si.sub.3 N.sub.4 layer 14. To avoid this problem it is a common practice in the semiconductor industry to plasma treat the surface with oxygen (O.sub.2) prior to patterning the photoresist.
One method of making shallow trench isolation (STI) is described in U.S. Pat. No. 5,863,827 to Joyner. The invention utilizes a method for making rounded trench corners to minimize the electric field effects when the circuit is powered on. However, Joyner does not address the need for forming photoresist patterns which are free of recesses 6 as described above with reference to FIG. 1.
However, there is still a need in the semiconductor industry to improve the Si.sub.3 N.sub.4 hard mask etch process while providing a more cost-effective manufacturing process.